1. Field of the Invention
The present invention relates to a group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof.
2. Description of the Background Art
In recent years, development of a group III nitride semiconductor substrate suitable as a substrate of various semiconductor devices such as an optical device and an electronic device, that has controlled resistivity, low dislocation density, and stable electric characteristic and/or optical characteristic, has been demanded.
As a method of significantly lowering dislocation density of a group III nitride semiconductor substrate, for example, Japanese Patent Laying-Open No. 2001-102307 (hereinafter, referred to as Patent Document 1) proposes a method of lowering dislocation density in a region other than a dislocation-concentrated region (referred to as low dislocation region here and hereinafter), by concentrating dislocations within crystals in the dislocation-concentrated region in the center portion of a pit by forming and maintaining facets inclosing the pit while crystals of a group III nitride semiconductor are grown on an underlying substrate.
In a GaN substrate obtained with the method according to Patent Document 1, however, the dislocation-concentrated region and the low dislocation region have been present in a mixed manner. In addition, in the low dislocation region as well, a region resulted from growth using the GaN facet as a growth surface (facet growth region) has become a region having low resistivity (low resistivity region), while a region resulted from growth using a GaN C face as a growth surface (C face growth region) has become a region having high resistivity (high resistivity region), and therefore, the low resistivity region and the high resistivity region have been present in a mixed manner. Therefore, in-plane distribution of dislocation density and resistivity of the GaN substrate obtained with the method according to Patent Document 1 has been great.
In addition, Japanese Patent Laying-Open No. 2000-068498 (hereinafter, referred to as Patent Document 2) proposes forming a group III nitride semiconductor layer having high resistivity by adding C (carbon) in high concentration during growth of crystals of a group III nitride semiconductor, while Japanese Patent Laying-Open No. 10-112438 (hereinafter, referred to as Patent Document 3) proposes growth of a p-type group III nitride semiconductor with fewer crystal defects. Moreover, Japanese Patent Laying-Open No. 11-026383 (hereinafter, referred to as Patent Document 4) proposes forming a buffer layer on a substrate, to which C has been added in advance in high concentration, in order to grow a group III nitride semiconductor with fewer crystal defects.
In any of Patent Documents 2 to 4 above, however, control of the resistivity has been difficult, and in-plane distribution of the resistivity has been great. In addition, in the group III nitride semiconductor layer or the group III nitride semiconductor layer substrate in any of Patent Documents 2 to 4 above, the dislocation density thereof cannot be as low as that of the GaN substrate obtained with the method according to Patent Document 1 above, and stability of the electric characteristic and/or optical characteristic has been insufficient.